1. Field of the Invention
The present invention concerns technology for forming, at a relatively low temperature of about 600xc2x0 C., polycrystalline semiconductor layers having outstanding crystalline properties. This technology is related particularly to a fabrication step capable of markedly improving the performance of thin-film semiconductor devices typified by polysilicon thin-film transistors.
2. Description of Related Art
Conventionally, a fabrication scheme such as that described below has been used when fabricating thin-film semiconductor devices such as polysilicon thin-film transistors (p-Si TFT) at low temperatures of approximately 600xc2x0 C. or less, where general-purpose glass substrates can be used. First, an amorphous silicon layer serving as a semiconductive layer is deposited on the substrate to a thickness of approximately 50 nm by low-pressure chemical vapor deposition (LPCVD). This amorphous layer is then irradiated with a XeCl excimer laser (wavelength: 308 nm) to form a polysilicon film (p-Si film). Since the absorption coefficient of the XeCl excimer laser in the amorphous silicon and polysilicon is large (0.139 nmxe2x88x921 and 0.149 nmxe2x88x921, respectively), 90% of the laser light impinging on the semiconductor films is absorbed at a depth of 15 nm or less from the surface. In addition, the absorption coefficient of amorphous silicon is approximately 7% smaller than the absorption coefficient of polysilicon. Next, a silicon oxide layer serving as a gate dielectric layer is formed by chemical vapor deposition (CVD) or by physical vapor deposition (PVD). Gate electrodes are then created using a material such as tantalum to form MOSFETsxe2x80x94field effect transistors consisting of a metal (gate), an oxide layer (gate dielectric layer) and a semiconductor (polysilicon layer). Finally, an interlevel dielectric layer is deposited on top of these layers; and, after contact holes are opened, a thin-film of metal interconnects is patterned, completing the thin-film semiconductor device.
However, controlling the energy density of the excimer laser light used in the conventional method of fabricating these thin-film semiconductor devices was difficult, and even slight fluctuations in the energy density caused the semiconductor layer to exhibit significant nonuniformity, even within the same substrate. Moreover, if the irradiated energy density was even slightly higher than the threshold value determined by film thickness and hydrogen content, the semiconductor layer incurred extensive damage, inviting marked deterioration of semiconductor characteristics and product yield. Therefore, the energy density of the laser light had to be set considerably lower than the optimum value to obtain a uniform polycrystalline semiconductor layer. For this reason, obtaining high quality polycrystalline thin films meant that an insufficient energy density could not be avoided. Furthermore, enlarging the grains that comprise the polycrystalline layer was difficult even if the laser was radiated at the optimum energy density; and a large number of defects were left in the layer. Therefore, to consistently fabricate thin-film semiconductor devices such as p-Si TFTs using the conventional fabrication method, the electrical characteristics of the finished thin-film semiconductor devices had to be sacrificed.
In view of the aforesaid situation, the purpose of the present invention is to provide a method for consistently fabricating extremely high quality thin-film semiconductor devices using a low temperature step of 600xc2x0 C. or less.
Following an overview of the present invention, the effects of the present invention and its fundamental principles will be described in detail.
The present invention includes a step for fabricating thin-film semiconductor devices having as the active layer a crystalline semiconductor film comprised mainly of silicon (Si) formed on a substrate; a semiconductor layer formation step in which a silicon oxide layer that serves as an underlevel protection layer is formed on the substrate if necessary and an amorphous semiconductor layer comprised mainly of silicon (Si) is deposited on top of the aforesaid underlevel protection layer or on the substrate; a solid phase crystallization step that crystallizes the amorphous semiconductor layer in a solid state and obtains a solid phase crystallization film; and a light irradiating step in which light from a pulsed laser is irradiated on the solid phase crystallization film thus obtained to obtain a crystalline semiconductor film; and is characterized by the fact that the wavelength of the pulsed laser beam used is greater than about 370 nm and less than about 710 nm. The absorption coefficient of said light in polysilicon is greater than the absorption coefficient in amorphous silicon. Moreover, the present invention is also characterized by the fact that the wavelength of the pulsed laser beam is greater than about 450 nm and less than about 650 nm. Accordingly, the absorption coefficient xcexcpSi of a pulsed laser beam in polysilicon is from approximately 10xe2x88x922 nmxe2x88x921 to 10xe2x88x923 nmxe2x88x921. In this case, if the film thickness of the semiconductor layer is taken to be d, it is desirable for the film thickness d(nm) and the absorption coefficient of the pulsed laser beam in polysilicon xcexcpSi (nmxe2x88x921) to satisfy the following relationship:
0.105xc2x7xcexcpSixe2x88x921 less than d less than 0.693xc2x7xcexcpSixe2x88x921.
Ideally, the following relationship is satisfied:
0.405xc2x7xcexcpSixe2x88x921 less than d less than 0.693xc2x7xcexcpSixe2x88x921.
In order for the present invention to be applicable to devices such as liquid crystal displays, it is desirable for the substrate to be transparent to visible light. Further, regardless of the application, it is also desirable for the substrate to be essentially transparent to the pulsed laser beam. xe2x80x9cEssentially transparentxe2x80x9d means that the absorption coefficient of the pulsed laser beam in the substrate is approximately one tenth the absorption coefficient in polycrystalline silicon or lower. Specifically, the absorption coefficient of the substrate xcexcSub should be approximately 10xe2x88x924 nmxe2x88x921 or lower. Normally, formation of the amorphous semiconductor layer mentioned above would include a deposition step by chemical vapor deposition (CVD). Within the chemical vapor deposition process category, low pressure chemical vapor deposition (LPCVD) and plasma-enhanced chemical vapor deposition are particularly applicable for deposition of amorphous semiconductor thin films; and it can be said further that amorphous semiconductor layer deposition in a high-vacuum low pressure chemical vapor deposition chamber or in a high-vacuum plasma-enhanced chemical vapor deposition chamber is ideal. A high-vacuum low pressure chemical vapor deposition chamber is one in which the background pressure immediately prior to semiconductor layer deposition is typically 5xc3x9710xe2x88x927 Torr or less, and that can achieve an atomic oxygen concentration within the amorphous semiconductor layer of approximately 2xc3x971016 cmxe2x88x923 or less even when the amorphous semiconductor layer is formed at a slow deposition rate of approximately 1.5 nm/min or less. Similarly, xe2x80x9chigh-vacuum plasma-enhanced chemical vapor deposition chamberxe2x80x9d refers to a deposition system in which the background pressure immediately before semiconductor layer deposition is typically 1xc3x9710xe2x88x926 Torr or less, and that can achieve an atomic oxygen concentration within the deposited amorphous semiconductor layer of approximately 2xc3x971016 cmxe2x88x923 or less even when the deposition rate of the amorphous semiconductor layer is approximately 1 nm/sec or less. When a YAG 2xcfx89 laser beam impinges on a semiconductor layer comprised mainly of silicon, it is preferable for the thickness of the semiconductor layer to be approximately 25 nm or more and approximately 165 nm or less, and, ideally, approximately 25 nm or more and approximately 95 nm or less.
The solid phase crystallization step is performed by inserting a substrate on which an amorphous semiconductor layer has been formed into an annealing furnace and maintaining a state of near thermal equilibrium, or is performed with a rapid thermal annealing system. When performed in an annealing furnace, the solid phase crystallization progresses at an annealing temperature of between approximately 400xc2x0 C. and 700xc2x0 C.
The ideal pulsed laser wavelength in the light irradiation step of the present invention is approximately 532 nm. For the pulsed laser beam, the harmonic of a solid-state laser having Q-switch oscillation (a Q-switched solid state laser) is preferred. Desirable as the lasing medium in a Q-switched solid state laser are crystals doped with Nd ions, crystals doped with Yb ions, glass doped with Nd ions, glass doped with Yb ions, and so forth. Specifically, therefore, it is best to use as a pulsed laser beam the second harmonic (wavelength: 532 nm) of a Q-switched Nd:YAG laser (abbreviated as YAG 2xcfx89), the second harmonic (wavelength: 532 nm) of a Q-switched Nd:YVO4 laser, the second harmonic (wavelength: 524 nm) of a Q-switched Nd:YLF laser, the second harmonic (wavelength: 515 nm) of a Q-switched Yb:YAG laser, and so forth.
The shape of the irradiated region on the semiconductor layer during the irradiation of the solid phase crystallization layer with a pulsed laser beam in the light irradiation step is either nearly rectangular or a line profile, having width W (xcexcm) and length L (mm). Within the irradiated region, the pulsed laser""s irradiation energy density has a roughly trapezoidal distribution along the length of the region. On the other hand, along the width of the region, it is preferable to have an irradiation energy density having either an approximately trapezoidal or approximately Gaussian distribution. It is desirable for the ratio (L/W) of the irradiation region length, L, to the width, W, to be greater than or equal to 100 and ideally greater than or equal to 1000.
It is preferable for the maximum gradient of the irradiation energy density along the width of the pulsed laser beam""s profile to have a value of 3 mJxc2x7cmxe2x88x922xc2x7xcexcmxe2x88x921 or higher. If the location at which the maximum value of the irradiated energy density gradient in the widthwise direction of this pulsed laser beam and the location at which the maximum value of the irradiated energy density in the widthwise direction of the pulsed laser beam are nearly coincident, it is even better for fabricating high quality thin-film semiconductor devices.
The beam width during irradiation is preferably approximately 1 xcexcm or more and approximately 6 xcexcm or less. The region on the solid phase crystallization layer irradiated by the pulsed laser beam is gradually shifted in the widthwise direction after each pulse until the entire surface of the substrate is completely irradiated. The widthwise direction of the irradiated area during pulsed laser beam irradiation is nearly parallel to the direction of electric current flow within the active layer of a finished, operating thin-film semiconductor device. During laser irradiation, the light irradiation step is performed such that any given point on the semiconductor layer is subjected to pulsed laser beam irradiation between 10 times and 80 times. The Irradiated energy density of the pulsed laser beam on the solid phase crystallization layer is of an intensity that melts at least the surface of the solid phase crystallization layer, and preferable still, is of an intensity that melts approximately two-thirds or more of the thickness of the solid phase crystallization layer. Conversely, the upper limit of irradiated energy density is below the intensity at which a portion of the solid phase crystallization layer is ablated, and ideally, is below the intensity at which the solid phase crystallization layer is melted over the entire thickness. Specifically, when light having a wavelength of approximately 532 nm is used as the pulsed laser beam, the irradiated energy density of the pulsed laser beam on the solid phase crystallization layer is approximately 100 mJxc2x7cmxe2x88x922 or less and approximately 1500 mJxc2x7cmxe2x88x922 or more, but preferably is between approximately 600 mJxc2x7cmxe2x88x922 or more and approximately 1500 mJxc2x7cmxe2x88x922 or less, or approximately 100 mJxc2x7cmxe2x88x922 or more and approximately 850 mJxc2x7cmxe2x88x922 or less, and ideally is between approximately 600 mJxc2x7cmxe2x88x922 or more and approximately 850 mJxc2x7cmxe2x88x922 or less.